The present invention relates to an internal reduced-voltage generator to be mounted in a semiconductor integrated circuit such as a dynamic random access memory (DRAM).
In recent years, semiconductor integrated circuits in which internal reduced-voltage generators are mounted have vigorously been developed for the purposes of decreasing their power consumption and of ensuring the reliability of their internal elements. In these semiconductor integrated circuits, the internal reduced-voltage generator generates an internal reduced voltages based on an external power-supply voltage VCC so that the internal elements thereof are supplied with the internal reduced voltage. For example, the circuit disclosed in Japanese Laid-Open Patent Publication No. 63-244217 provides an internal reduced voltage which is less dependent on VCC.
In Japanese Laid-Open Patent Publication No. 64-13292, on the other hand, there is disclosed a DRAM provided with a self-refreshment function of use on the occasion of battery back up that requires a power-saving operation. In the DRAM, the switching from the normal operation mode to a self-refreshment mode is carried out by the application of a RAS (row address strobe) and CAS (column address strobe) with a specified timing. To drive its internal elements, however, the conventional DRAM uses the same voltage in the self-refreshing period, which requires the power-saving operation, as that used in the normal operation.
There is also proposed a voltage limiter for use in a DRAM which is suitable for burn-in (M. Horiguchi et al., Technical Report of IEICE, ICD91-129, 1991, pp. 25-32). With the voltage limiter, an internal reduced voltage is stably provided in the normal operation and, by simply raising VCC, a voltage to be used in a burn-in acceleration test, which is higher than the foregoing internal reduced voltage, is automatically supplied to the internal elements. To perform this function, the voltage limiter comprises a first reference voltage generator for generating the internal reduced voltage to be used in the normal operation (VRN regulator), first trimmer for adjusting the internal reduced voltage, second reference voltage generator for generating the higher voltage to be used in the burn-in acceleration test (VRB regulator), and second trimmer for adjusting the higher voltage.
Since the internal elements of the conventional DRAMs are operated, even in the self-refreshing period, with the same voltage used in the normal operation, it is impossible to sufficiently reduce the power consumption of the DRAMs during the battery back up.
Moreover, since the aforesaid voltage regulator comprises the two independent circuits for generating the two different reference voltages, the power consumption and layout area of the DRAM in which the voltage regulator is mounted are thereby increased. Furthermore, the provision of the two trimmers has spurs the increase in power consumption and layout area.